Superior packaging know-how continues to make waves this yr after being a outstanding spotlight in 2023 and is intently tied to the fortunes of a brand new semiconductor business star: chiplets. IDTechEx’s new report titled “Superior Semiconductor Packaging 2024-2034: Forecasts, Applied sciences, Purposes” explores superior packaging’s present panorama whereas going into element about rising applied sciences resembling 2.5D and 3D packaging.
Determine 1 2.5D and 3D packaging facilitate higher interconnection densities for chips serving purposes like AI, knowledge facilities, and 5G. Supply: IDTechEx
After fabs manufacture chips on silicon wafers by varied superior processes, packaging amenities obtain accomplished wafers from fabs, minimize them into particular person chips, assemble or “package deal” them into ultimate merchandise, and check them for efficiency and high quality. These packaged chips are then shipped to unique tools producers (OEMs).
That’s a part of the normal semiconductor manufacturing worth chain wherein engineers construct system-on-chips (SoCs) on silicon wafers after which transfer them to standard packaging processes. Enter chiplets, manufactured of particular person system modalities as standalone chips or chiplets on a wafer, then integrating these separate functionalities right into a system by superior packaging.
This premise brings superior packaging to the forefront of semiconductor manufacturing innovation. In reality, the way forward for chiplets is intertwined with developments in superior packaging, the place 2.5D and 3D applied sciences are quickly taking form to facilitate the industrial realization of chiplets.
2.5D and 3D packaging
Whereas 1D and 2D semiconductor packaging applied sciences proceed to dominate many purposes, future developments relate to 2.5D and 3D packaging to realize the conclusion of more-than-Moore semiconductor realm. These applied sciences leverage wafer-level integration for miniaturization of elements, resulting in higher interconnection densities.
Determine 2 Superior packaging methods like 2.5D and 3D enhance system bandwidth and energy effectivity by growing I/O routing density and decreasing I/O bump measurement. Supply: Siemens EDA
2.5D know-how, which facilitates bigger packaging areas, mandates a shift from silicon interposers to silicon bridges or different options resembling high-density fan-out. However packaging elements of various supplies collectively additionally results in many challenges. The IDTechEx report asserts that discovering the correct supplies and manufacturing methods is crucial for two.5D packaging adoption.
Subsequent, 3D packaging brings new constructions into play. That features integrating one lively die on high of one other lively die and decreasing bump pitch distance. This 3D method—referred to as hybrid bonding—can be utilized for purposes resembling CMOS picture sensors, 3D NAND flash and HBM reminiscence, and chiplets. Nevertheless, like 2.5 packaging, 3D packaging entails manufacturing and price challenges as methods like hybrid bonding demand new high-quality instruments and supplies.
OSAT and EDA traction
The event of an ecosystem usually affords very important clues about the way forward for a nascent know-how like superior packaging. Whereas challenges abound, current semiconductor business bulletins bode nicely for IC packaging capabilities within the 2.5 and 3D eras.
Amkor, a serious outsourced semiconductor meeting and check (OSAT) service supplier, is investing roughly $2 billion to construct a sophisticated packaging and check facility in Peoria, Arizona. The 55-acre web site can be prepared for manufacturing in a few years.
Then there’s Silicon Field, a sophisticated panel-level packaging foundry specializing in chiplet integration, packaging, and testing. After organising a sophisticated packaging facility in Singapore, the corporate is constructing a brand new web site in Northen Italy to higher serve fabs in Europe.
EDA toolmakers are additionally being attentive to this promising new panorama. For example, Siemens EDA is working intently with South Korean OSAT nepes to develop its IC packaging capabilities for the 3D-IC period. Siemens EDA is offering nepes instruments to sort out the broad vary of complicated thermal, mechanical, and different challenges related to growing superior 3D-IC packages.
Determine 3 Innovator3D IC software program delivers a quick, predictable path for the planning and heterogeneous integration of ASICs and chiplets utilizing 2.5D and 3D packaging applied sciences. Supply: Siemens EDA
Siemens EDA’s Innovator3D IC toolset proven above makes use of a hierarchical gadget planning method to deal with the huge complexity of superior 2.5D/3D built-in designs with hundreds of thousands of pins. Right here, designs are represented as geometrically partitioned areas with attributes controlling elaboration and implementation strategies. That, in flip, permits crucial updates to be shortly carried out whereas matching analytic methods to particular areas, avoiding excessively lengthy execution instances.
In the meantime, new supplies and manufacturing processes will proceed to be developed to confront the challenges going through 2.5D and 3D packaging. Maybe one other replace earlier than Christmas will present higher readability on the place superior packaging know-how stands in 2024 and past.
Associated Content material
- How the Worlds of Chiplets and Packaging Intertwine
- TSMC crunch heralds good days for superior packaging
- Intel and FMD’s Roadmap for 3D Heterogeneous Integration
- Heterogeneous Integration and the Evolution of IC Packaging
- Samsung’s superior packaging pivot with Nvidia manufacturing win
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