The everyday regulator output community

Many voltage regulator chips, each linear and switching, use the identical fundamental two-resistor community for output voltage programming. Determine 1 illustrates this function in a typical switching (buck kind) regulator, see R1 and R2, the place:

Vout = Vsense(R1/R2 + 1) = 0.8v(11.5 + 1) = 10v

Determine 1 A typical regulator output programming community the place the Vsense suggestions node and values for R1 varies from kind to kind.

Quantitatively, the Vsense suggestions node voltage varies from kind to kind and really helpful values for R1 can fluctuate too, however the topology doesn’t. Most conform faithfully to Determine 1. This de facto uniformity is helpful in case your software includes PWM management of Vout. 

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The three-component PWM-to-regulator answer

Determine 2 exhibits the straightforward three-component answer that the above topology makes doable. Word, the PWM obligation issue (DF) is from 0 to 1, the place:

Vout = Vsense(R1/(R2/DF) + 1) = DF(11.5)0.8 + 0.8 = DF*9.2 + 0.8v

Determine 2 Three elements comprise a circuit for linear regulator programming with PWM.

To introduce linear PWM management to the Determine 1 regulator, all that’s required is so as to add three discrete parts: the PWM swap Q1, and the ripple filter capacitors C1 and C2. Word that Vout will go to Vsense(C1/C2 + 1) = 10v for about 6 ms throughout energy up whereas C1 and C2 are charging, however that must be okay.

The C2 capacitance required for 1 lsb (0.4%) PWM ripple attenuation is C2 = 2^(N-2)/(R1*Fpwm), the place N is variety of PWM bits, and Fpwm is the PWM frequency (10 kHz illustrated).

Then, to keep away from messing with U1’s designed loop achieve, presumably decreasing stability, C1 = C2*R2/R1. This capacitance ratio additionally supplies safety for U1’s Vsense enter, because it ensures that even a sudden wanting Vout to floor can’t drive Vsense dangerously adverse.

 This mix of time constants yields a first-order 8-bit settling time of T₈ = R1C2ln(256) = 37ms. Extra on this prolonged quantity shortly.

A cool function of this straightforward topology is that, not like many different schemes for digital energy provide management, solely the precision of R1, R2, and the regulator’s inner voltage reference matter for regulation accuracy. Precision is subsequently unbiased of exterior voltage sources, e.g., logic rails. Precision, measured as proportion of Vout, can be unbiased of Df, and stays equal to Vsense precision (e.g., ±1%) for all output voltages.

Rushing up the settling time

What if a 37-ms settling time is just too prolonged on your software? What should you wouldn’t thoughts investing a pair extra elements to hurry it up? Determine 3 exhibits what.

Determine 3 Add R3 and C3 to get analog ripple subtraction, second-order filtering, and a 7-ms settling time. The image “*” represents a precision of 1% or higher.

First disclosed in EDN Design Concept (DI), “Cancel PWM DAC ripple with analog subtraction,” a thrifty technique to implement second-order PWM ripple filtering is thru the analog subtraction of the AC part within the logic inverse of the PWM sign from the DC end result. Determine 3 exhibits how that may be completed by merely including R3 and C3 to the Determine 2 topology. Word that the impedance ratios of the added elements are equal to the ratio of the 5-Vpp PWM sign at Q1’s gate to the 0.8-Vpp logic complement at its drain = 5v/0.8v = 6.5.  Because of this R3 = 6.5*R2 and C3 = C2/6.5.

In closing: This DI revises an earlier submission, “Three discretes suffice to interface PWM to switching regulators.” My thanks go to commenters oldrev, Ashutosh Sapre, and Val Filimonov for his or her useful recommendation and constructive criticism. And particular thanks go to editor Shaukat for her creation of an setting pleasant to the DI teamwork that made this doable.

Stephen Woodward’s relationship with EDN’s DI column goes again fairly a great distance. Over 100 submissions have been accepted since his first contribution again in 1974.

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