- Improves PCIe design productiveness utilizing a better and streamlined workflow with simulation-driven digital compliance check options
- Helps design exploration and report technology that speeds chiplet sign integrity evaluation and UCIe compliance verification to extend designer productiveness and time-to-market
Keysight Applied sciences, Inc. introduces System Designer for PCIe, a brand new product within the Superior Design System (ADS) product suite that helps simulation workflows primarily based on trade requirements for high-speed, high-frequency digital designs. System Designer for PCIe is an clever design atmosphere for modeling and simulating the most recent Peripheral Element Interconnect Categorical (PCIe) Gen5 and Gen6 programs. Keysight can also be enhancing its digital design automation (EDA) platform by including new options to the prevailing Chiplet PHY Designer instrument to estimate chiplet die-to-die hyperlink margin efficiency and Voltage Switch Perform (VTF) compliance measurement.
PCIe is a flexible and important interface customary throughout a variety of electronics trade segments as a result of its high-speed knowledge switch capabilities, scalability, and flexibility. Adoption spans from on a regular basis client electronics to specialised functions in high-performance computing and important infrastructure programs.
Complicated PCIe designs help multi-link and multi-lane programs that contain a posh evaluation setup between RootComplex and Finish-Level, generally incorporating mid-channel repeaters. Designers spend an inordinate period of time getting ready simulations which might be susceptible to errors. Simulations usually lack vendor-specific algorithmic modeling interface (AMI) simulation fashions, that are required early within the design cycle for design area exploration. Designers additionally want assurance that their prototype design will move compliance testing earlier than {hardware} fabrication.
Productiveness, Workflow, and Compliance Enchancment Options
- The System Designer for PCIe automates the setup for multi-link, multi-lane, and multi-level (PAM4) PCIe programs utilizing a sensible design atmosphere. It simplifies simulation setup and reduces time-to-first-insight.
- The PCIe AMI modeler, which helps NRZ and PAM4 modulations, facilitates fast AMI mannequin technology wanted for PCIe system evaluation. The AMI Mannequin Builder provides designers a wizard-driven AMI mannequin technology workflow to quickly create fashions for each transmitters (Tx) and receivers (Rx).
- Streamlined, simulation-driven digital compliance testing permits designers to make sure design high quality. The built-in, simulation-driven PCIe compliance check workflow reduces design prices by minimizing design iterations and shortening time-to-market.
Chiplet PHY Designer Enhancements
- Chiplet PHY Designer is the EDA trade’s first simulation resolution for Common Chiplet Interconnect Categorical (UCIe) requirements, enabling predictions of die-to-die hyperlink margin, VTF for channel compliance evaluation, and forwarded clock functionality. Chiplet PHY Designer consists of new design exploration and report technology options that speed up sign integrity evaluation and compliance verification to enhance designer productiveness and time-to-market.
Hee-Soo Lee, Director of Excessive-Velocity Digital section, Keysight EDA, stated, “We proceed to develop our standards-driven workflow strategy to help our prospects. Our high-speed digital product portfolio is main the EDA trade with probably the most correct and superior simulation software program for sign integrity evaluation and compliance check validation. Digital requirements reminiscent of PCIe and UCIe are vital to the efficiency of digital programs. Designers utilizing our PCIe and UCIe simulation options of their workflows can shift left their growth cycle to save lots of vital time and price.”
